This invention relates to computer cache memories, and particularly to cache memories capable of executing multiple memory instructions simultaneously. One feature of the invention permits load and store coherence with out-of-order issuance capabilities.
In computer organizations, it is desirable to achieve instruction issue rates of at least one, and preferably more than one, instruction per clock cycle. One technique to accomplish this is to issue multiple instructions during each clock cycle. For example, a multiple instruction issue unit might issue instructions in the order as they are found in the memory. A more general approach has been to issue instructions from a pool of instructions, thereby permitting issuance of instructions within a defined instructional window, provided certain instruction conditions are met (register conflicts, bus conflicts, arithmetic unit conflicts, etc.). It is desirable in such instances to rename registers before entering the instruction window, thereby removing all destination register conflicts.
As used herein, the term "load" shall refer to loading or reading data from a memory, and the term "store" shall refer to storing data or writing data into a memory. Thus, a "load address" is the address of the memory location from which data is loaded or read, and a "store address" is the address of the memory location where data is stored or written.
Pipeline architecture contemplates permitting a single processor to commence execution of an instruction before execution of a previous instruction has been completed. An instruction may be partially or fully executed out of normal sequence as long as the instruction does not require the results of an unexecuted instruction. In the case of a load instruction, for example, previous store instructions had to be fully executed before the load instruction could be executed.
One problem with prior multiple instruction issue organizations is that load and store operations could not be done completely out of order. If a load instruction issued before a preceding store instruction in a prior instruction organization, the load instruction would receive improper data because the store should have been completed first. To avoid conflict conditions, prior instruction issue techniques have required stores be completed before issuing following loads.
A typical instruction mix will include approximately 25% load instructions and 10% store instructions. A single pipeline cache is not adequate for instruction issue rates greater than two instructions per clock. Consequently, it is desirable to employ a dual data cache pipeline structure.